Agnisys to Unveil AI, NoC and DFT Automation at DAC 2026

Agnisys will showcase new automation tools at DAC 2026 in Long Beach, California, including IDS-AI, IDS-NoC and advanced DFT research. The company says the tools are designed to speed chip design, improve verification and help teams manage growing SoC complexity.

Why it matters: - Chip designs are becoming more complex because of AI workloads, chiplet architectures and safety-critical applications. - Agnisys is pitching automation that spans specification, design generation, verification, testability, validation and documentation. - The goal is faster sign-off, higher quality and lower manual effort across SoC development.

What happened: - Agnisys said it will showcase IDS-AI, IDS-NoC and advanced Design-for-Test automation at the 63rd Design Automation Conference, or DAC 2026. - DAC 2026 runs July 27-29 in Long Beach, California. - The company will present its DFT research on July 28, 2026, in Seaside Room 7. - Agnisys will also exhibit at Booth #1557. - Engineering leaders, architects, verification engineers and SoC designers are invited to the booth for live demonstrations.

The details: - IDS-AI is the company’s agentic AI framework for semiconductor design intent. - IDS-AI automates specification creation, RTL generation and verification in one workflow. - Agnisys says the framework is designed to move teams from golden specification creation to RTL sign-off faster. - IDS-AI is meant to help teams catch defects earlier and improve correct-by-construction accuracy. - IDS-NoC automates the creation of scalable, deadlock-free Network-on-Chip fabrics. - The tool is aimed at AI accelerators, automotive platforms and multi-core SoCs. - IDS-NoC generates open SystemVerilog RTL fabrics instead of requiring teams to hand-build routers and interfaces. - Agnisys will present research on Design-Aware Test Points, or DATP, built into the SystemRDL-to-RTL flow. - Early adopters have seen up to 4x better Test Coverage Per Flip-Flop and 50% fewer top-level ATPG patterns, according to the company. - The DATP talk will be presented by Veerabhadrarao Vasa and Rajesh Gottumukkala of Google and Freddy Nunez of Agnisys. - Agnisys says its AI-driven solutions reduce token costs while keeping results predictable and correct-by-construction. - The company positions its tools for startups building AI chips and established semiconductor companies working on complex SoCs. - Visitors can schedule a meeting by emailing marcom@agnisys.com or by visiting the DAC 2026 event page. - Agnisys also lists social accounts on LinkedIn, Facebook, YouTube and X.

Between the lines: - The announcement shows Agnisys leaning into agentic AI as a design-flow tool rather than a standalone assistant. - The company is also tying AI messaging to practical semiconductor pain points such as verification, test coverage and integration complexity. - The DFT research suggests Agnisys is trying to position automation earlier in the design flow, not just at the end.

What's next: - Agnisys will run live demonstrations during DAC 2026. - The company plans an exclusive technical webinar on August 20, 2026, titled “AI-Based CSR Signoff Verification for Faster SoC Development.” - The webinar will show how AI-driven automation can speed CSR verification, improve verification quality and eliminate manual signoff processes. - Additional registration details will be posted on the Agnisys website.

The bottom line: - Agnisys is using DAC 2026 to make a broader case that deterministic AI and automation can shorten semiconductor development cycles without sacrificing correctness.